This invention relates generally to a parallel asynchronous sample rate reducer and, more particularly to an asynchronous sample rate reducer for converting a synchronous parallel digital input signal into a parallel digital output signal with an average aggregate sample rate that is asynchronous with respect to the input sample clock rate.
Existing communication systems typically include modulators and demodulators designed to operate at relatively high speeds. In order to further improve the throughput of modulation/demodulation systems, conventional systems use modulated parallel, digital signals for transmission and demodulation upon receipt. Thus, the throughput of such communication systems depends upon the speed of modulation and demodulation. Present implementation of the modulation systems include sample rate reducers. Sample rate reducers typically process one sample during each clock cycle. An example of such a system may be found with reference to xe2x80x9cInterpolation in Digital Modemsxe2x80x94Part 1: Fundamentalsxe2x80x9d, Floyd Gardner, IEEE Transactions On Communications, Vol. 41, No. 3, Mar. 3, 1993, pp. 501-507. The Gardner reference describes an approach for using interpolation in digital modems to expedite the demodulation process.
In accordance with the present invention there is provided a high data rate demodulator.
Further in accordance with the present invention there is provided a parallel asynchronous sample rate reducer that converts a synchronous parallel digital input signal into a parallel digital output signal having an average aggregate sample rate that is asynchronous with respect to the input sample clock rate.
Also in accordance with the present invention there is provided a digital demodulator having an input sample rate that is asynchronous with respect to the demodulated output data rate.
In accordance with the teachings of the present invention, a sample rate reducer processes a parallel input data stream sampled at a sample clock rate into a parallel output data stream at a sample rate that is asynchronous with respect to the sample clock rate. The sample rate reducer includes a parallel phase accumulator for receiving a sample control signal that varies in accordance with a desired sample frequency. The parallel phase accumulator generates a parallel phase accumulator value having a plurality of components, each component including a sample number and a fractional phase value. A logic controller receives the parallel phase accumulator value and a frequency control signal, and the logic controller generates a parallel interval control value defining a desired time delay between an input sample and a required output sample. The logic controller also generates a parallel control build value which includes the phase accumulator value sample number with multiple, identical sample numbers reduced to a single sample. A parallel interpolator receives the parallel input stream of data and generates a parallel interpolator output data stream. The parallel interpolator output data stream includes interpolated values at the intervals defined by the interval control value. A parallel word builder receives the control build value from the logic controller and the parallel interpolator output data stream, and assembles valid samples from the parallel interpolator output data stream to form the parallel output data stream comprising interpolated values corresponding to consecutively numbered samples.